library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mustervergleich is
    Port ( A1 : in STD_LOGIC;
           A0 : in STD_LOGIC;
           B1 : in STD_LOGIC;
           B0 : in STD_LOGIC;
           C : out STD_LOGIC);
end mustervergleich;

architecture Behavioral of mustervergleich is
begin
    C <= (A1 xnor B1) and (A0 xnor B0);
end Behavioral;

Code 0-1: VHDL-Datei

## FPGA Configuration I/O Options
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

## Slide Switches
set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS12} [get_ports {A1}];
set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS12} [get_ports {A0}];
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS12} [get_ports {B1}];
set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS12} [get_ports {B0}];

## LEDs
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {C}]

Code 0-2: Constraints-Datei

...
-- Vier D-FlipFlops instanziieren
--	FLIP3: entity FDCE_instanz
	FLIP3: FDCE
	    port map(D => sig_d(3), C => clock1Hz, CLR => not all_reset, Q => sig_q(3), CE => eins);
	FLIP2: FDCE
	    port map(D => sig_d(2), C => clock1Hz, CLR => not all_reset, Q => sig_q(2), CE => eins);
	FLIP1: FDCE
	    port map(D => sig_d(1), C => clock1Hz, CLR => not all_reset, Q => sig_q(1), CE => eins);
	FLIP0: FDCE
	    port map(D => sig_d(0), C => clock1Hz, CLR => not all_reset, Q => sig_q(0), CE => eins);
...

Code 0-3: Erstes Flipflop referenziert auf ein selbst geschriebenes Modul, die anderen sind Standardelemente der UNISIM-Library.

Wie macht man das, wenn man eine Entity in einem anderen
VHDL-File definiert:

library xil_defaultLib;
use xil_defaultLib.NAME_DER_ENTITY;

ODER:
ev. geht auch work.NAME_EIGENE_ENTITY

Code 0-4: Ergänzende Angaben