library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity blink2026 is
    Port ( btn0 : in STD_LOGIC;
           ld0 : out STD_LOGIC);
end blink2026;

architecture Behavioral of blink2026 is

begin

ld0 <= btn0;
end Behavioral;

Code 0-1: blink2026.vhd, VHDL-Code.

# Buttons
set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { btn0 }]; #IO_L15N_T2_DQS_34 Sch=btn[0]

# LEDs
set_property -dict { PACKAGE_PIN J1    IOSTANDARD LVCMOS33 } [get_ports { ld0 }]; #IO_L8N_T1_34 Sch=led[0]

Code 0-2: blink2026.xdc, Constraints-Code, gewonnen aus Cmod-S7-25-Master.xdc.

Add sources
finish => Aufforderung für Behavioural öffnet automatisch

run synthesis

run implementation  ... wird vorgeschlagen

open implemented design ... wird vorgeschlagen

Code 0-3: Ablauf Synthese von oben nach unten.