Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: LIN Target Device: xc3s250e
Project ID (random number) ee0eb98de10045fc9825da25affded4b.FB424E275835BFCCCA5E89EE8CCEDBAC.2 Target Package: tq144
Registration ID 211070429_0_0_814 Target Speed: -4
Date Generated 2018-06-05T20:49:10 Tool Flow ISE
 
User Environment
OS Name Ubuntu OS Release Ubuntu 16.04.3 LTS
CPU Name Intel(R) Core(TM) i5-4210M CPU @ 2.60GHz CPU Speed 3197.473 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=15
  • 10-bit adder=4
  • 11-bit adder=3
  • 14-bit adder=1
  • 16-bit adder=2
  • 7-bit adder=1
  • 9-bit adder=4
 Comparators=17
  • 10-bit comparator greatequal=1
  • 10-bit comparator lessequal=2
  • 11-bit comparator greatequal=3
  • 11-bit comparator lessequal=6
  • 16-bit comparator greatequal=1
  • 16-bit comparator lessequal=2
  • 22-bit comparator less=1
  • 7-bit comparator greatequal=1
 Counters=1
  • 22-bit up counter=1
 Multipliers=13
  • 3x6-bit multiplier=4
  • 3x8-bit multiplier=5
  • 7x5-bit multiplier=1
  • 7x7-bit multiplier=1
  • 9x6-bit multiplier=1
  • 9x8-bit multiplier=1
 Registers=1
  • Flip-Flops=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=8
  • AGG_IO=8
  • AGG_SLICE=146
  • NUM_4_INPUT_LUT=267
  • NUM_BONDED_IBUF=5
  • NUM_BONDED_IOB=3
  • NUM_BUFGMUX=1
  • NUM_CYMUX=137
  • NUM_LUT_RT=39
  • NUM_MULT18X18SIO=4
  • NUM_SLICEL=146
  • NUM_SLICE_FF=23
  • NUM_XOR=103
 		NetStatistics
  • NumNets_Active=347
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMDUMMY=82
  • NumNodesOfType_Active_CLKPIN=12
  • NumNodesOfType_Active_CNTRLPIN=12
  • NumNodesOfType_Active_DOUBLE=447
  • NumNodesOfType_Active_DUMMY=751
  • NumNodesOfType_Active_DUMMYBANK=19
  • NumNodesOfType_Active_DUMMYESC=5
  • NumNodesOfType_Active_GLOBAL=8
  • NumNodesOfType_Active_HFULLHEX=12
  • NumNodesOfType_Active_HLONG=5
  • NumNodesOfType_Active_HUNIHEX=56
  • NumNodesOfType_Active_INPUT=913
  • NumNodesOfType_Active_IOBOUTPUT=5
  • NumNodesOfType_Active_OMUX=217
  • NumNodesOfType_Active_OUTPUT=284
  • NumNodesOfType_Active_PREBXBY=210
  • NumNodesOfType_Active_VFULLHEX=17
  • NumNodesOfType_Active_VLONG=2
  • NumNodesOfType_Active_VUNIHEX=63
  • NumNodesOfType_Vcc_BRAMDUMMY=42
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=48
  • NumNodesOfType_Vcc_PREBXBY=6
  • NumNodesOfType_Vcc_VCCOUT=19
 SiteStatistics
  • IBUF-DIFFM=2
  • IBUF-DIFFMI=1
  • IBUF-DIFFS=2
  • IOB-DIFFM=2
  • SLICEL-SLICEM=53
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=5
  • IBUF_INBUF=5
  • IBUF_PAD=5
  • IOB=3
  • IOB_OUTBUF=3
  • IOB_PAD=3
  • MULT18X18SIO=4
  • MULT18X18SIO_MULT18X18SIO=4
  • SLICEL=146
  • SLICEL_C1VDD=10
  • SLICEL_C2VDD=10
  • SLICEL_CYMUXF=72
  • SLICEL_CYMUXG=65
  • SLICEL_F=143
  • SLICEL_F5MUX=14
  • SLICEL_FFX=11
  • SLICEL_FFY=12
  • SLICEL_G=124
  • SLICEL_GNDF=32
  • SLICEL_GNDG=30
  • SLICEL_XORF=53
  • SLICEL_XORG=50
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:1] [LVCMOS33:4]
  • PULL=[PULLUP:4]
 IOB
  • O1=[O1_INV:0] [O1:3]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:3]
 IOB_PAD
  • DRIVEATTRBOX=[12:3]
  • IOATTRBOX=[LVCMOS33:3]
  • SLEW=[SLOW:3]
 MULT18X18SIO
  • CEA=[CEA_INV:0] [CEA:4]
  • CEB=[CEB_INV:0] [CEB:4]
  • CEP=[CEP:4] [CEP_INV:0]
  • CLK=[CLK:4] [CLK_INV:0]
  • RSTA=[RSTA:4] [RSTA_INV:0]
  • RSTB=[RSTB:4] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:4]
 MULT18X18SIO_MULT18X18SIO
  • AREG=[0:4]
  • BREG=[0:4]
  • B_INPUT=[DIRECT:4]
  • CEA=[CEA_INV:0] [CEA:4]
  • CEB=[CEB_INV:0] [CEB:4]
  • CEP=[CEP:4] [CEP_INV:0]
  • CLK=[CLK:4] [CLK_INV:0]
  • PREG=[0:4]
  • PREG_CLKINVERSION=[0:4]
  • RSTA=[RSTA:4] [RSTA_INV:0]
  • RSTB=[RSTB:4] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:4]
 SLICEL
  • BX=[BX_INV:0] [BX:29]
  • BY=[BY:0] [BY_INV:1]
  • CE=[CE:1] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:61]
  • CLK=[CLK:12] [CLK_INV:0]
  • SR=[SR:11] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:72] [0_INV:0]
  • 1=[1_INV:0] [1:72]
 SLICEL_CYMUXG
  • 0=[0:65] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:14] [S0_INV:0]
 SLICEL_FFX
  • CK=[CK:11] [CK_INV:0]
  • D=[D:11] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:11]
  • FFX_SR_ATTR=[SRLOW:11]
  • LATCH_OR_FF=[FF:11]
  • SR=[SR:11] [SR_INV:0]
  • SYNC_ATTR=[SYNC:11]
 SLICEL_FFY
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:12] [CK_INV:0]
  • D=[D:11] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:12]
  • FFY_SR_ATTR=[SRLOW:12]
  • LATCH_OR_FF=[FF:12]
  • SR=[SR:11] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:1] [SYNC:11]
 SLICEL_XORF
  • 1=[1_INV:0] [1:53]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 IBUF
  • I=5
  • PAD=5
 IBUF_INBUF
  • IN=5
  • OUT=5
 IBUF_PAD
  • PAD=5
 IOB
  • O1=3
  • PAD=3
 IOB_OUTBUF
  • IN=3
  • OUT=3
 IOB_PAD
  • PAD=3
 MULT18X18SIO
  • A0=4
  • A1=4
  • A10=4
  • A11=4
  • A12=4
  • A13=4
  • A14=4
  • A15=4
  • A16=4
  • A17=4
  • A2=4
  • A3=4
  • A4=4
  • A5=4
  • A6=4
  • A7=4
  • A8=4
  • A9=4
  • B0=4
  • B1=4
  • B10=4
  • B11=4
  • B12=4
  • B13=4
  • B14=4
  • B15=4
  • B16=4
  • B17=4
  • B2=4
  • B3=4
  • B4=4
  • B5=4
  • B6=4
  • B7=4
  • B8=4
  • B9=4
  • CEA=4
  • CEB=4
  • CEP=4
  • CLK=4
  • P0=4
  • P1=4
  • P10=4
  • P11=4
  • P12=3
  • P13=2
  • P14=1
  • P2=4
  • P3=4
  • P4=4
  • P5=4
  • P6=4
  • P7=4
  • P8=4
  • P9=4
  • RSTA=4
  • RSTB=4
  • RSTP=4
 MULT18X18SIO_MULT18X18SIO
  • A0=4
  • A1=4
  • A10=4
  • A11=4
  • A12=4
  • A13=4
  • A14=4
  • A15=4
  • A16=4
  • A17=4
  • A2=4
  • A3=4
  • A4=4
  • A5=4
  • A6=4
  • A7=4
  • A8=4
  • A9=4
  • B0=4
  • B1=4
  • B10=4
  • B11=4
  • B12=4
  • B13=4
  • B14=4
  • B15=4
  • B16=4
  • B17=4
  • B2=4
  • B3=4
  • B4=4
  • B5=4
  • B6=4
  • B7=4
  • B8=4
  • B9=4
  • CEA=4
  • CEB=4
  • CEP=4
  • CLK=4
  • P0=4
  • P1=4
  • P10=4
  • P11=4
  • P12=3
  • P13=2
  • P14=1
  • P2=4
  • P3=4
  • P4=4
  • P5=4
  • P6=4
  • P7=4
  • P8=4
  • P9=4
  • RSTA=4
  • RSTB=4
  • RSTP=4
 SLICEL
  • BX=29
  • BY=1
  • CE=1
  • CIN=61
  • CLK=12
  • COUT=65
  • F1=139
  • F2=109
  • F3=90
  • F4=61
  • G1=123
  • G2=100
  • G3=73
  • G4=55
  • SR=11
  • X=110
  • XB=2
  • XQ=11
  • Y=79
  • YQ=12
 SLICEL_C1VDD
  • 1=10
 SLICEL_C2VDD
  • 1=10
 SLICEL_CYMUXF
  • 0=72
  • 1=72
  • OUT=72
  • S0=72
 SLICEL_CYMUXG
  • 0=65
  • 1=65
  • OUT=65
  • S0=65
 SLICEL_F
  • A1=139
  • A2=109
  • A3=90
  • A4=61
  • D=143
 SLICEL_F5MUX
  • F=14
  • G=14
  • OUT=14
  • S0=14
 SLICEL_FFX
  • CK=11
  • D=11
  • Q=11
  • SR=11
 SLICEL_FFY
  • CE=1
  • CK=12
  • D=12
  • Q=12
  • SR=11
 SLICEL_G
  • A1=123
  • A2=100
  • A3=73
  • A4=55
  • D=124
 SLICEL_GNDF
  • 0=32
 SLICEL_GNDG
  • 0=30
 SLICEL_XORF
  • 0=53
  • 1=53
  • O=53
 SLICEL_XORG
  • 0=50
  • 1=50
  • O=50
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 109 109 0 0 0 0 0
map 139 139 0 0 0 0 0
ngdbuild 142 142 0 0 0 0 0
par 139 121 18 0 0 0 0
trce 121 121 0 0 0 0 0
xst 308 306 0 0 0 0 0
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2018-06-05T19:38:43 PROP_intWbtProjectID=FB424E275835BFCCCA5E89EE8CCEDBAC
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s250e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=tq144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDE=1 NGDBUILD_NUM_FDR=22 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=4 NGDBUILD_NUM_INV=15 NGDBUILD_NUM_LUT1=39 NGDBUILD_NUM_LUT2=46
NGDBUILD_NUM_LUT3=47 NGDBUILD_NUM_LUT4=116 NGDBUILD_NUM_MULT18X18SIO=4 NGDBUILD_NUM_MUXCY=137
NGDBUILD_NUM_MUXF5=14 NGDBUILD_NUM_OBUF=3 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=103
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDE=1 NGDBUILD_NUM_FDR=22 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=4 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=15 NGDBUILD_NUM_LUT1=39
NGDBUILD_NUM_LUT2=46 NGDBUILD_NUM_LUT3=47 NGDBUILD_NUM_LUT4=116 NGDBUILD_NUM_MULT18X18SIO=4
NGDBUILD_NUM_MUXCY=137 NGDBUILD_NUM_MUXF5=14 NGDBUILD_NUM_OBUF=3 NGDBUILD_NUM_PULLUP=4
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=103
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s250e-4-tq144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5