neuro1 Project Status (06/05/2018 - 13:34:13)
Project File: neuro1.xise Parser Errors: No Errors
Module Name: neuro1 Implementation State: Programming File Generated
Target Device: xc3s250e-4tq144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1 Warning (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 23 4,896 1%  
Number of 4 input LUTs 12 4,896 1%  
Number of occupied Slices 19 2,448 1%  
    Number of Slices containing only related logic 19 19 100%  
    Number of Slices containing unrelated logic 0 19 0%  
Total Number of 4 input LUTs 35 4,896 1%  
    Number used as logic 12      
    Number used as a route-thru 23      
Number of bonded IOBs 8 108 7%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.02      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentDi. Jun 5 13:33:38 201801 Warning (0 new)0
Translation ReportCurrentDi. Jun 5 13:33:48 2018000
Map ReportCurrentDi. Jun 5 13:33:54 2018002 Infos (0 new)
Place and Route ReportCurrentDi. Jun 5 13:34:03 2018002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentDi. Jun 5 13:34:05 2018006 Infos (0 new)
Bitgen ReportCurrentDi. Jun 5 13:34:11 2018000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentDi. Jun 5 13:34:12 2018
WebTalk Log FileCurrentDi. Jun 5 13:34:13 2018

Date Generated: 06/05/2018 - 13:34:13