neuround Project Status (05/23/2019 - 10:13:00)
Project File:	neuround.xise	Parser Errors:	No Errors
Module Name:	neuround	Implementation State:	Programming File Generated
Target Device:	xc3s250e-4tq144	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	3 Warnings (0 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of 4 input LUTs	55	4,896	1%
Number of occupied Slices	33	2,448	1%
Number of Slices containing only related logic	33	33	100%
Number of Slices containing unrelated logic	0	33	0%
Total Number of 4 input LUTs	63	4,896	1%
Number used as logic	55
Number used as a route-thru	8
Number of bonded IOBs	3	108	2%
Number of MULT18X18SIOs	2	12	16%
Average Fanout of Non-Clock Nets	2.11

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Do. Mai 23 10:12:30 2019	0	3 Warnings (0 new)	0
Translation Report	Current	Do. Mai 23 10:12:37 2019	0	0	0
Map Report	Current	Do. Mai 23 10:12:42 2019	0	0	2 Infos (0 new)
Place and Route Report	Current	Do. Mai 23 10:12:49 2019	0	0	1 Info (0 new)
Power Report
Post-PAR Static Timing Report	Current	Do. Mai 23 10:12:53 2019	0	0	6 Infos (0 new)
Bitgen Report	Current	Do. Mai 23 10:12:58 2019	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Do. Mai 23 10:12:59 2019
WebTalk Log File	Current	Do. Mai 23 10:13:00 2019

Date Generated: 05/23/2019 - 10:13:00