uhr Project Status (06/19/2017 - 12:33:00)
Project File: uhr.xise Parser Errors: No Errors
Module Name: uhr Implementation State: Programming File Generated
Target Device: xc3s250e-4tq144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
11 Warnings (4 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 75 4,896 1%  
Number of 4 input LUTs 86 4,896 1%  
Number of occupied Slices 67 2,448 2%  
    Number of Slices containing only related logic 67 67 100%  
    Number of Slices containing unrelated logic 0 67 0%  
Total Number of 4 input LUTs 109 4,896 2%  
    Number used as logic 86      
    Number used as a route-thru 23      
Number of bonded IOBs 21 108 19%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.44      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMo. Jun 19 12:32:29 2017011 Warnings (4 new)7 Infos (0 new)
Translation ReportCurrentMo. Jun 19 12:32:35 2017000
Map ReportCurrentMo. Jun 19 12:32:40 2017002 Infos (0 new)
Place and Route ReportCurrentMo. Jun 19 12:32:50 2017002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMo. Jun 19 12:32:53 2017006 Infos (0 new)
Bitgen ReportCurrentMo. Jun 19 12:32:58 2017000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMo. Jun 19 12:32:59 2017
WebTalk Log FileCurrentMo. Jun 19 12:33:00 2017

Date Generated: 06/19/2017 - 12:33:00