SCHIEBEREGISTER Project Status | |||
Project File: | schieberegister.ise | Current State: | Programming File Generated |
Module Name: | schieberegister |
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No Errors |
Target Device: | xc3s250e-4tq144 |
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10 Warnings |
Product Version: | ISE 9.1i |
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Mi Okt 21 11:19:23 2015 |
SCHIEBEREGISTER Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 26 | 4,896 | 1% | |
Number of 4 input LUTs | 11 | 4,896 | 1% | |
Logic Distribution | ||||
Number of occupied Slices | 21 | 2,448 | 1% | |
Number of Slices containing only related logic | 21 | 21 | 100% | |
Number of Slices containing unrelated logic | 0 | 21 | 0% | |
Total Number of 4 input LUTs | 34 | 4,896 | 1% | |
Number used as logic | 11 | |||
Number used as a route-thru | 23 | |||
Number of bonded IOBs | 7 | 108 | 6% | |
IOB Flip Flops | 1 | |||
Number of GCLKs | 1 | 24 | 4% | |
Total equivalent gate count for design | 447 | |||
Additional JTAG gate count for IOBs | 336 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | Mi Okt 21 11:18:47 2015 | 0 | 3 Warnings | 1 Info |
Translation Report | Current | Mi Okt 21 11:18:51 2015 | 0 | 0 | 0 |
Map Report | Current | Mi Okt 21 11:18:54 2015 | 0 | 2 Warnings | 3 Infos |
Place and Route Report | Current | Mi Okt 21 11:18:58 2015 | 0 | 4 Warnings | 2 Infos |
Static Timing Report | Current | Mi Okt 21 11:19:00 2015 | 0 | 0 | 3 Infos |
Bitgen Report | Current | Mi Okt 21 11:19:23 2015 | 0 | 1 Warning | 0 |