Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: LIN Target Device: xc3s250e
Project ID (random number) ee0eb98de10045fc9825da25affded4b.4A4D71EB1180DF278EE980C109AC95B6.2 Target Package: tq144
Registration ID 211070429_0_0_814 Target Speed: -4
Date Generated 2015-10-14T15:01:02 Tool Flow ISE
 
User Environment
OS Name Ubuntu OS Release Ubuntu 14.04 LTS
CPU Name Intel(R) Core(TM) i5-4210M CPU @ 2.60GHz CPU Speed 2000.000 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=2
  • 16-bit comparator less=2
Counters=1
  • 16-bit up counter=1
MiscellaneousStatistics
  • AGG_BONDED_IO=4
  • AGG_IO=4
  • AGG_SLICE=19
  • NUM_4_INPUT_LUT=38
  • NUM_BONDED_IBUF=3
  • NUM_BONDED_IOB=1
  • NUM_BUFGMUX=1
  • NUM_CYMUX=37
  • NUM_LUT_RT=21
  • NUM_SLICEL=19
  • NUM_SLICE_FF=16
  • NUM_XOR=16
NetStatistics
  • NumNets_Active=42
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=8
  • NumNodesOfType_Active_CNTRLPIN=8
  • NumNodesOfType_Active_DOUBLE=12
  • NumNodesOfType_Active_DUMMY=61
  • NumNodesOfType_Active_DUMMYESC=3
  • NumNodesOfType_Active_GLOBAL=8
  • NumNodesOfType_Active_HFULLHEX=2
  • NumNodesOfType_Active_HUNIHEX=1
  • NumNodesOfType_Active_INPUT=78
  • NumNodesOfType_Active_IOBOUTPUT=3
  • NumNodesOfType_Active_OMUX=37
  • NumNodesOfType_Active_OUTPUT=37
  • NumNodesOfType_Active_PREBXBY=12
  • NumNodesOfType_Active_VFULLHEX=4
  • NumNodesOfType_Active_VLONG=1
  • NumNodesOfType_Active_VUNIHEX=3
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=2
  • NumNodesOfType_Vcc_PREBXBY=2
  • NumNodesOfType_Vcc_VCCOUT=3
SiteStatistics
  • IBUF-DIFFM=1
  • IBUF-DIFFMI=1
  • IBUF-DIFFS=1
  • IOB-DIFFM=1
  • SLICEL-SLICEM=8
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=3
  • IBUF_INBUF=3
  • IBUF_PAD=3
  • IOB=1
  • IOB_OUTBUF=1
  • IOB_PAD=1
  • SLICEL=19
  • SLICEL_C1VDD=5
  • SLICEL_C2VDD=1
  • SLICEL_CYMUXF=19
  • SLICEL_CYMUXG=18
  • SLICEL_F=19
  • SLICEL_FFX=8
  • SLICEL_FFY=8
  • SLICEL_G=19
  • SLICEL_GNDF=10
  • SLICEL_GNDG=12
  • SLICEL_XORF=8
  • SLICEL_XORG=8
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:1] [LVCMOS33:2]
  • PULL=[PULLUP:2]
IOB
  • O1=[O1_INV:0] [O1:1]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:1]
IOB_PAD
  • DRIVEATTRBOX=[12:1]
  • IOATTRBOX=[LVCMOS33:1]
  • SLEW=[FAST:1]
SLICEL
  • BX=[BX_INV:0] [BX:3]
  • CIN=[CIN_INV:0] [CIN:16]
  • CLK=[CLK:8] [CLK_INV:0]
  • SR=[SR:8] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:19] [0_INV:0]
  • 1=[1_INV:0] [1:19]
SLICEL_CYMUXG
  • 0=[0:18] [0_INV:0]
SLICEL_FFX
  • CK=[CK:8] [CK_INV:0]
  • D=[D:8] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:8]
  • FFX_SR_ATTR=[SRLOW:8]
  • LATCH_OR_FF=[FF:8]
  • SR=[SR:8] [SR_INV:0]
  • SYNC_ATTR=[SYNC:8]
SLICEL_FFY
  • CK=[CK:8] [CK_INV:0]
  • D=[D:8] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:8]
  • FFY_SR_ATTR=[SRLOW:8]
  • LATCH_OR_FF=[FF:8]
  • SR=[SR:8] [SR_INV:0]
  • SYNC_ATTR=[SYNC:8]
SLICEL_XORF
  • 1=[1_INV:0] [1:8]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=3
  • PAD=3
IBUF_INBUF
  • IN=3
  • OUT=3
IBUF_PAD
  • PAD=3
IOB
  • O1=1
  • PAD=1
IOB_OUTBUF
  • IN=1
  • OUT=1
IOB_PAD
  • PAD=1
SLICEL
  • BX=3
  • CIN=16
  • CLK=8
  • COUT=18
  • F1=19
  • F2=6
  • F3=4
  • F4=1
  • G1=19
  • G2=7
  • G3=4
  • SR=8
  • XQ=8
  • YQ=8
SLICEL_C1VDD
  • 1=5
SLICEL_C2VDD
  • 1=1
SLICEL_CYMUXF
  • 0=19
  • 1=19
  • OUT=19
  • S0=19
SLICEL_CYMUXG
  • 0=18
  • 1=18
  • OUT=18
  • S0=18
SLICEL_F
  • A1=19
  • A2=6
  • A3=4
  • A4=1
  • D=19
SLICEL_FFX
  • CK=8
  • D=8
  • Q=8
  • SR=8
SLICEL_FFY
  • CK=8
  • D=8
  • Q=8
  • SR=8
SLICEL_G
  • A1=19
  • A2=7
  • A3=4
  • D=19
SLICEL_GNDF
  • 0=10
SLICEL_GNDG
  • 0=12
SLICEL_XORF
  • 0=8
  • 1=8
  • O=8
SLICEL_XORG
  • 0=8
  • 1=8
  • O=8
 
Tool Usage
Command Line History
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • ngdbuild -ise <ise_file> <fname>.ngd
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s250e-tq144-4 -cm area -pr b -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s250e-tq144-4 -cm area -pr b -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s250e-tq144-4 -cm area -pr b -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s250e-tq144-4 -cm area -pr b -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s250e-tq144-4 -cm area -pr b -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr b -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 4 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr b -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 4 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 2 2 0 0 0 0 0
map 2 2 0 0 0 0 0
ngdbuild 2 2 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 2 2 0 0 0 0 0
xst 2 2 0 0 0 0 0
 
Project Statistics
PROP_CompxlibOverwriteLib=true PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_ImpactProjectFile=changed
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PostTrceFastPath=false
PROP_PreTrceFastPath=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/testbench_servo PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_XPowerOptLoadXMLFile=changed PROP_XPowerOptOutputFile=changed
PROP_intProjectCreationTimestamp=2015-10-08T20:15:34 PROP_intWbtProjectID=4A4D71EB1180DF278EE980C109AC95B6
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_selectedSimRootSourceNode_behav=work.testbench_servo
PROP_xilxMapPackRegInto=For Inputs and Outputs PROP_xilxPostTrceRpt=Error Report
PROP_xilxPreTrceRpt=Error Report PROP_AutoTop=true
PROP_DevFamily=Spartan3E PROP_MapEffortLevel=Standard
PROP_mapSmartGuideFileName=changed PROP_parSmartGuideFileName=changed
PROP_DevDevice=xc3s250e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=tq144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=VHDL
FILE_UCF=1 FILE_VHDL=2
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDR=16 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2
NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT1=21 NGDBUILD_NUM_LUT2=5 NGDBUILD_NUM_LUT3=7
NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_MUXCY=37 NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=16
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDR=16 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT1=21 NGDBUILD_NUM_LUT2=5
NGDBUILD_NUM_LUT3=7 NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_MUXCY=37 NGDBUILD_NUM_OBUF=1
NGDBUILD_NUM_PULLUP=2 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=16
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s250e-4-tq144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=ieee
Fuse Resource Usage=1590 ms, 90696 KB
Total Signals=11
Total Nets=7
Total Blocks=5
Total Processes=6
Total Simulation Time=1 us
Simulation Resource Usage=0.1 sec, 140529 KB
Simulation Mode=gui
Hardware CoSim=0