Project Statistics |
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PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_ImpactProjectFile=changed |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PostTrceFastPath=false |
PROP_PreTrceFastPath=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/testbench_servo |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_XPowerOptLoadXMLFile=changed |
PROP_XPowerOptOutputFile=changed |
PROP_intProjectCreationTimestamp=2015-10-08T20:15:34 |
PROP_intWbtProjectID=4A4D71EB1180DF278EE980C109AC95B6 |
PROP_intWbtProjectIteration=2 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.testbench_servo |
PROP_xilxMapPackRegInto=For Inputs and Outputs |
PROP_xilxPostTrceRpt=Error Report |
PROP_xilxPreTrceRpt=Error Report |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3E |
PROP_MapEffortLevel=Standard |
PROP_mapSmartGuideFileName=changed |
PROP_parSmartGuideFileName=changed |
PROP_DevDevice=xc3s250e |
PROP_DevFamilyPMName=spartan3e |
PROP_DevPackage=tq144 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=VHDL |
FILE_UCF=1 |
FILE_VHDL=2 |