servo Project Status
Project File: servo.xise Parser Errors: No Errors
Module Name: servo Implementation State: Programming File Generated
Target Device: xc3s250e-4tq144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1 Warning (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 16 4,896 1%  
Number of 4 input LUTs 17 4,896 1%  
Number of occupied Slices 19 2,448 1%  
    Number of Slices containing only related logic 19 19 100%  
    Number of Slices containing unrelated logic 0 19 0%  
Total Number of 4 input LUTs 38 4,896 1%  
    Number used as logic 17      
    Number used as a route-thru 21      
Number of bonded IOBs 4 108 3%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.58      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMi. Okt 14 15:00:31 201501 Warning (0 new)0
Translation ReportCurrentMi. Okt 14 15:00:39 2015000
Map ReportCurrentMi. Okt 14 15:00:44 2015001 Info (0 new)
Place and Route ReportCurrentMi. Okt 14 15:00:53 2015002 Infos (0 new)
Static Timing ReportCurrentMi. Okt 14 15:00:55 2015006 Infos (0 new)
Bitgen ReportCurrentMi. Okt 14 15:01:01 2015000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMi. Okt 14 15:01:02 2015
WebTalk Log FileCurrentMi. Okt 14 15:01:03 2015

Date Generated: 10/23/2015 - 16:40:44