mustervergleich Project Status | |||
Project File: | mustervergleich.xise | Parser Errors: | No Errors |
Module Name: | mustervergleich | Implementation State: | Programming File Generated |
Target Device: | xc3s250e-4tq144 |
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No Errors |
Product Version: | ISE 14.7 |
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2 Warnings (0 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of 4 input LUTs | 1 | 4,896 | 1% | ||
Number of occupied Slices | 1 | 2,448 | 1% | ||
Number of Slices containing only related logic | 1 | 1 | 100% | ||
Number of Slices containing unrelated logic | 0 | 1 | 0% | ||
Total Number of 4 input LUTs | 1 | 4,896 | 1% | ||
Number of bonded IOBs | 5 | 108 | 4% | ||
Total equivalent gate count for design | 6 | ||||
Additional JTAG gate count for IOBs | 240 |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mo. Sep 14 14:46:26 2015 | 0 | 0 | 0 | |
Translation Report | Current | Mo. Sep 14 14:47:58 2015 | 0 | 0 | 0 | |
Map Report | Current | Mo. Sep 14 14:48:00 2015 | 0 | 2 Warnings (0 new) | 2 Infos (0 new) | |
Place and Route Report | Current | Mo. Sep 14 14:48:04 2015 | 0 | 0 | 1 Info (0 new) | |
Static Timing Report | Current | Mo. Sep 14 14:48:06 2015 | 0 | 0 | 3 Infos (0 new) | |
Bitgen Report | Current | Mo. Sep 14 14:48:10 2015 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated |