mustervergleich Project Status
Project File: mustervergleich.xise Parser Errors: No Errors
Module Name: mustervergleich Implementation State: Programming File Generated
Target Device: xc3s250e-4tq144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
2 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
(Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 1 4,896 1%  
Number of occupied Slices 1 2,448 1%  
    Number of Slices containing only related logic 1 1 100%  
    Number of Slices containing unrelated logic 0 1 0%  
Total Number of 4 input LUTs 1 4,896 1%  
Number of bonded IOBs 5 108 4%  
Total equivalent gate count for design 6      
Additional JTAG gate count for IOBs 240      
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMo. Sep 14 14:46:26 2015000
Translation ReportCurrentMo. Sep 14 14:47:58 2015000
Map ReportCurrentMo. Sep 14 14:48:00 201502 Warnings (0 new)2 Infos (0 new)
Place and Route ReportCurrentMo. Sep 14 14:48:04 2015001 Info (0 new)
Static Timing ReportCurrentMo. Sep 14 14:48:06 2015003 Infos (0 new)
Bitgen ReportCurrentMo. Sep 14 14:48:10 2015000
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 10/07/2015 - 12:45:06