| BINAERZAEHLER Project Status | |||
| Project File: | binaerzaehler.ise | Current State: | Programming File Generated |
| Module Name: | binaerzaehler |
|
No Errors |
| Target Device: | xc3s250e-4tq144 |
|
No Warnings |
| Product Version: | ISE 9.1i |
|
Fr Sep 11 12:05:08 2015 |
| BINAERZAEHLER Partition Summary | |||
| No partition information was found. |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops | 26 | 4,896 | 1% | |
| Number of 4 input LUTs | 16 | 4,896 | 1% | |
| Logic Distribution | ||||
| Number of occupied Slices | 20 | 2,448 | 1% | |
| Number of Slices containing only related logic | 20 | 20 | 100% | |
| Number of Slices containing unrelated logic | 0 | 20 | 0% | |
| Total Number of 4 input LUTs | 39 | 4,896 | 1% | |
| Number used as logic | 16 | |||
| Number used as a route-thru | 23 | |||
| Number of bonded IOBs | 5 | 108 | 4% | |
| Number of GCLKs | 1 | 24 | 4% | |
| Total equivalent gate count for design | 469 | |||
| Additional JTAG gate count for IOBs | 240 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints Met | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | Fr Sep 11 12:04:51 2015 | 0 | 0 | 0 |
| Translation Report | Current | Fr Sep 11 12:04:54 2015 | 0 | 0 | 0 |
| Map Report | Current | Fr Sep 11 12:04:57 2015 | 0 | 0 | 3 Infos |
| Place and Route Report | Current | Fr Sep 11 12:05:01 2015 | 0 | 0 | 2 Infos |
| Static Timing Report | Current | Fr Sep 11 12:05:03 2015 | 0 | 0 | 3 Infos |
| Bitgen Report | Current | Fr Sep 11 12:05:08 2015 | 0 | 0 | 0 |