Xilinx Design Summary

BLINKLED Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	23	4,896	1%
Number of 4 input LUTs	11	4,896	1%
Logic Distribution
Number of occupied Slices	18	2,448	1%
Number of Slices containing only related logic	18	18	100%
Number of Slices containing unrelated logic	0	18	0%
Total Number of 4 input LUTs	34	4,896	1%
Number used as logic	11
Number used as a route-thru	23
Number of bonded IOBs	2	108	1%
Number of GCLKs	1	24	4%
Total equivalent gate count for design	415
Additional JTAG gate count for IOBs	96

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met