Device Usage Statistics Report

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta	FALSE	build_version	3064766
date_generated	Tue Apr 20 20:44:30 2021	os_platform	LIN64
product_version	Vivado v2020.2 (64-bit)	project_id	2412961febf6426e82c67a467f457d65
project_iteration	1	random_id	bcfae8310c755bf7ad97b7045d4a4511
registration_id	211070429_0_0_814	route_design	TRUE
target_device	xc7a200t	target_family	artix7
target_package	fbg484	target_speed	-1
tool_flow	Vivado

user_environment
cpu_name	AMD Ryzen 7 4700U with Radeon Graphics	cpu_speed	1305.690 MHz
os_name	Ubuntu	os_release	Ubuntu 20.04.1 LTS
system_ram	16.000 GB	total_processors	1

vivado_usage

gui_handlers
basedialog_apply=1	basedialog_cancel=2	basedialog_ok=21	basedialog_yes=1
constraintschooserpanel_add_files=1	filesetpanel_file_set_panel_tree=2	flownavigatortreepanel_flow_navigator_tree=5	fpgachooser_category=3
fpgachooser_family=3	fpgachooser_fpga_table=4	gettingstartedview_create_new_project=1	gettingstartedview_open_project=1
logmonitor_monitor=1	mainmenumgr_checkpoint=2	mainmenumgr_edit=2	mainmenumgr_file=4
mainmenumgr_ip=2	mainmenumgr_project=1	mainmenumgr_text_editor=1	pacommandnames_close_project=1
pacommandnames_run_bitgen=2	projectnamechooser_choose_project_location=1	projectnamechooser_project_name=1	rdicommands_settings=2
settingsprojectgeneralpage_choose_device_for_your_project=2	srcchooserpanel_add_directories=1

java_command_handlers
addsources=1	closeproject=1	newproject=1	openproject=1
runbitgen=3	runimplementation=3	runsynthesis=3	showview=1
toolssettings=2

other_data
guimode=2

project_data
constraintsetcount=1	core_container=false	currentimplrun=impl_1	currentsynthesisrun=synth_1
default_library=xil_defaultlib	designmode=RTL	export_simulation_activehdl=1	export_simulation_ies=1
export_simulation_modelsim=1	export_simulation_questa=1	export_simulation_riviera=1	export_simulation_vcs=1
export_simulation_xsim=1	implstrategy=Vivado Implementation Defaults	launch_simulation_activehdl=0	launch_simulation_ies=0
launch_simulation_modelsim=0	launch_simulation_questa=0	launch_simulation_riviera=0	launch_simulation_vcs=0
launch_simulation_xsim=0	simulator_language=VHDL	srcsetcount=8	synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL	target_simulator=XSim	totalimplruns=1	totalsynthesisruns=2

unisim_transformation

post_unisim_transformation
bufg=1	carry4=18	fdce=4	fdpe=1
fdre=233	fdse=5	gnd=11	ibuf=10
lut1=13	lut2=25	lut3=36	lut4=22
lut5=65	lut6=60	muxf7=5	obuf=6
ramb18e1=1	ramb36e1=2	vcc=9	xadc=1

pre_unisim_transformation
bufg=1	carry4=18	fdce=4	fdpe=1
fdre=233	fdse=5	gnd=11	ibuf=10
lut1=13	lut2=25	lut3=36	lut4=22
lut5=65	lut6=60	muxf7=5	obuf=6
ramb18e1=1	ramb36e1=2	vcc=9	xadc=1

phys_opt_design_post_place

command_line_options
-aggressive_hold_fix=default::[not_specified]	-bram_register_opt=default::[not_specified]	-clock_opt=default::[not_specified]	-critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified]	-directive=default::[not_specified]	-dsp_register_opt=default::[not_specified]	-effort_level=default::[not_specified]
-fanout_opt=default::[not_specified]	-hold_fix=default::[not_specified]	-insert_negative_edge_ffs=default::[not_specified]	-multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified]	-restruct_opt=default::[not_specified]	-retime=default::[not_specified]	-rewire=default::[not_specified]
-shift_register_opt=default::[not_specified]	-uram_register_opt=default::[not_specified]	-verbose=default::[not_specified]	-vhfn=default::[not_specified]

power_opt_design

command_line_options_spo
-cell_types=default::all	-clocks=default::[not_specified]	-exclude_cells=default::[not_specified]	-include_cells=default::[not_specified]

usage
bram_ports_augmented=0	bram_ports_newly_gated=0	bram_ports_total=6	flow_state=default
slice_registers_augmented=0	slice_registers_newly_gated=0	slice_registers_total=243	srls_augmented=0
srls_newly_gated=0	srls_total=0

ip_statistics

xadc_wiz_v3_3_0/1
channel_averaging=None	component_name=xadc_wiz_0	core_container=NA	dclk_frequency=100
enable_axi=false	enable_axi4stream=false	enable_busy=true	enable_convst=false
enable_convstclk=false	enable_dclk=true	enable_drp=true	enable_eoc=true
enable_eos=true	enable_vbram_alaram=false	enable_vccaux_alaram=trueenable_vccpaux_alaram=false	enable_vccddro_alaram=false
enable_vccint_alaram=false	enable_vccpint_alaram=false	iptotal=1	ot_alaram=false
sequencer_mode=on	startup_channel_selection=contineous_sequence	timing_mode=continuous	user_temp_alaram=true

report_drc

command_line_options
-append=default::[not_specified]	-checks=default::[not_specified]	-fail_on=default::[not_specified]	-force=default::[not_specified]
-format=default::[not_specified]	-internal=default::[not_specified]	-internal_only=default::[not_specified]	-max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified]	-name=default::[not_specified]	-no_waivers=default::[not_specified]	-return_string=default::[not_specified]
-ruledecks=default::[not_specified]	-upgrade_cw=default::[not_specified]	-waived=default::[not_specified]

results
cfgbvs-1=1

report_utilization

clocking
bufgctrl_available=32	bufgctrl_fixed=0	bufgctrl_used=2	bufgctrl_util_percentage=6.25
bufhce_available=120	bufhce_fixed=0	bufhce_used=0	bufhce_util_percentage=0.00
bufio_available=40	bufio_fixed=0	bufio_used=0	bufio_util_percentage=0.00
bufmrce_available=20	bufmrce_fixed=0	bufmrce_used=0	bufmrce_util_percentage=0.00
bufr_available=40	bufr_fixed=0	bufr_used=0	bufr_util_percentage=0.00
mmcme2_adv_available=10	mmcme2_adv_fixed=0	mmcme2_adv_used=0	mmcme2_adv_util_percentage=0.00
plle2_adv_available=10	plle2_adv_fixed=0	plle2_adv_used=0	plle2_adv_util_percentage=0.00

dsp
dsps_available=740	dsps_fixed=0	dsps_used=0	dsps_util_percentage=0.00

io_standard
blvds_25=0	diff_hstl_i=0	diff_hstl_i_18=0	diff_hstl_ii=0
diff_hstl_ii_18=0	diff_hsul_12=0	diff_mobile_ddr=0	diff_sstl135=0
diff_sstl135_r=0	diff_sstl15=0	diff_sstl15_r=0	diff_sstl18_i=0
diff_sstl18_ii=0	hstl_i=0	hstl_i_18=0	hstl_ii=0
hstl_ii_18=0	hsul_12=0	lvcmos12=1	lvcmos15=0
lvcmos18=0	lvcmos25=0	lvcmos33=1	lvds_25=0
lvttl=0	mini_lvds_25=0	mobile_ddr=0	pci33_3=0
ppds_25=0	rsds_25=0	sstl135=0	sstl135_r=0
sstl15=0	sstl15_r=0	sstl18_i=0	sstl18_ii=0
tmds_33=0

memory
block_ram_tile_available=365	block_ram_tile_fixed=0	block_ram_tile_used=2.5	block_ram_tile_util_percentage=0.68
ramb18_available=730	ramb18_fixed=0	ramb18_used=1	ramb18_util_percentage=0.14
ramb18e1_only_used=1	ramb36_fifo_available=365	ramb36_fifo_fixed=0	ramb36_fifo_used=2
ramb36_fifo_util_percentage=0.55	ramb36e1_only_used=2

primitives
bufg_functional_category=Clock	bufg_used=2	carry4_functional_category=CarryLogic	carry4_used=18
fdce_functional_category=Flop & Latch	fdce_used=4	fdpe_functional_category=Flop & Latch	fdpe_used=1
fdre_functional_category=Flop & Latch	fdre_used=233	fdse_functional_category=Flop & Latch	fdse_used=5
ibuf_functional_category=IO	ibuf_used=10	lut1_functional_category=LUT	lut1_used=13
lut2_functional_category=LUT	lut2_used=25	lut3_functional_category=LUT	lut3_used=36
lut4_functional_category=LUT	lut4_used=22	lut5_functional_category=LUT	lut5_used=65
lut6_functional_category=LUT	lut6_used=60	muxf7_functional_category=MuxFx	muxf7_used=5
obuf_functional_category=IO	obuf_used=6	ramb18e1_functional_category=Block Memory	ramb18e1_used=1
ramb36e1_functional_category=Block Memory	ramb36e1_used=2	xadc_functional_category=Others	xadc_used=1

slice_logic
f7_muxes_available=66900	f7_muxes_fixed=0	f7_muxes_used=5	f7_muxes_util_percentage=<0.01
f8_muxes_available=33450	f8_muxes_fixed=0	f8_muxes_used=0	f8_muxes_util_percentage=0.00
lut_as_logic_available=133800	lut_as_logic_fixed=0	lut_as_logic_used=175	lut_as_logic_util_percentage=0.13
lut_as_memory_available=46200	lut_as_memory_fixed=0	lut_as_memory_used=0	lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=267600	register_as_flip_flop_fixed=0	register_as_flip_flop_used=243	register_as_flip_flop_util_percentage=0.09
register_as_latch_available=267600	register_as_latch_fixed=0	register_as_latch_used=0	register_as_latch_util_percentage=0.00
slice_luts_available=133800	slice_luts_fixed=0	slice_luts_used=175	slice_luts_util_percentage=0.13
slice_registers_available=267600	slice_registers_fixed=0	slice_registers_used=243	slice_registers_util_percentage=0.09
lut_as_distributed_ram_fixed=0	lut_as_distributed_ram_used=0	lut_as_logic_available=133800	lut_as_logic_fixed=0
lut_as_logic_used=175	lut_as_logic_util_percentage=0.13	lut_as_memory_available=46200	lut_as_memory_fixed=0
lut_as_memory_used=0	lut_as_memory_util_percentage=0.00	lut_as_shift_register_fixed=0	lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0	lut_in_front_of_the_register_is_unused_used=57	lut_in_front_of_the_register_is_used_fixed=57	lut_in_front_of_the_register_is_used_used=16
register_driven_from_outside_the_slice_fixed=16	register_driven_from_outside_the_slice_used=73	register_driven_from_within_the_slice_fixed=73	register_driven_from_within_the_slice_used=170
slice_available=33450	slice_fixed=0	slice_registers_available=267600	slice_registers_fixed=0
slice_registers_used=243	slice_registers_util_percentage=0.09	slice_used=92	slice_util_percentage=0.28
slicel_fixed=0	slicel_used=54	slicem_fixed=0	slicem_used=38
unique_control_sets_available=33450	unique_control_sets_fixed=33450	unique_control_sets_used=28	unique_control_sets_util_percentage=0.08
using_o5_and_o6_fixed=0.08	using_o5_and_o6_used=46	using_o5_output_only_fixed=46	using_o5_output_only_used=0
using_o6_output_only_fixed=0	using_o6_output_only_used=129

specific_feature
bscane2_available=4	bscane2_fixed=0	bscane2_used=0	bscane2_util_percentage=0.00
capturee2_available=1	capturee2_fixed=0	capturee2_used=0	capturee2_util_percentage=0.00
dna_port_available=1	dna_port_fixed=0	dna_port_used=0	dna_port_util_percentage=0.00
efuse_usr_available=1	efuse_usr_fixed=0	efuse_usr_used=0	efuse_usr_util_percentage=0.00
frame_ecce2_available=1	frame_ecce2_fixed=0	frame_ecce2_used=0	frame_ecce2_util_percentage=0.00
icape2_available=2	icape2_fixed=0	icape2_used=0	icape2_util_percentage=0.00
pcie_2_1_available=1	pcie_2_1_fixed=0	pcie_2_1_used=0	pcie_2_1_util_percentage=0.00
startupe2_available=1	startupe2_fixed=0	startupe2_used=0	startupe2_util_percentage=0.00
xadc_available=1	xadc_fixed=1	xadc_used=1	xadc_util_percentage=100.00

synthesis

command_line_options
-assert=default::[not_specified]	-bufg=default::12	-cascade_dsp=default::auto	-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto	-debug_log=default::[not_specified]	-directive=default::default	-fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt	-fsm_extraction=default::auto	-gated_clock_conversion=default::off	-generic=default::[not_specified]
-include_dirs=default::[not_specified]	-keep_equivalent_registers=default::[not_specified]	-lint=default::[not_specified]	-max_bram=default::-1
-max_bram_cascade_height=default::-1	-max_dsp=default::-1	-max_uram=default::-1	-max_uram_cascade_height=default::-1
-mode=default::default	-name=default::[not_specified]	-no_lc=default::[not_specified]	-no_srlextract=default::[not_specified]
-no_timing_driven=default::[not_specified]	-os=default::[not_specified]	-part=xc7a200tfbg484-1	-resource_sharing=default::auto
-retiming=default::[not_specified]	-rtl=default::[not_specified]	-rtl_skip_constraints=default::[not_specified]	-rtl_skip_ip=default::[not_specified]
-seu_protect=default::none	-sfcu=default::[not_specified]	-shreg_min_size=default::3	-top=top
-verilog_define=default::[not_specified]

usage
elapsed=00:00:19s	hls_ip=0	memory_gain=64.031MB	memory_peak=2366.391MB