| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
0 |
269,200 |
0% |
|
| Number of Slice LUTs |
1 |
134,600 |
1% |
|
| Number used as logic |
1 |
134,600 |
1% |
|
| Number using O6 output only |
1 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
0 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
0 |
46,200 |
0% |
|
| Number used exclusively as route-thrus |
0 |
|
|
|
| Number of occupied Slices |
1 |
33,650 |
1% |
|
| Number of LUT Flip Flop pairs used |
1 |
|
|
|
| Number with an unused Flip Flop |
1 |
1 |
100% |
|
| Number with an unused LUT |
0 |
1 |
0% |
|
| Number of fully used LUT-FF pairs |
0 |
1 |
0% |
|
Number of slice register sites lost
to control set restrictions |
0 |
269,200 |
0% |
|
| Number of bonded IOBs |
5 |
285 |
1% |
|
| Number of LOCed IOBs |
5 |
5 |
100% |
|
| Number of RAMB36E1/FIFO36E1s |
0 |
365 |
0% |
|
| Number of RAMB18E1/FIFO18E1s |
0 |
730 |
0% |
|
| Number of BUFG/BUFGCTRLs |
0 |
32 |
0% |
|
| Number of IDELAYE2/IDELAYE2_FINEDELAYs |
0 |
500 |
0% |
|
| Number of ILOGICE2/ILOGICE3/ISERDESE2s |
0 |
500 |
0% |
|
| Number of ODELAYE2/ODELAYE2_FINEDELAYs |
0 |
|
|
|
| Number of OLOGICE2/OLOGICE3/OSERDESE2s |
0 |
500 |
0% |
|
| Number of PHASER_IN/PHASER_IN_PHYs |
0 |
40 |
0% |
|
| Number of PHASER_OUT/PHASER_OUT_PHYs |
0 |
40 |
0% |
|
| Number of BSCANs |
0 |
4 |
0% |
|
| Number of BUFHCEs |
0 |
120 |
0% |
|
| Number of BUFRs |
0 |
40 |
0% |
|
| Number of CAPTUREs |
0 |
1 |
0% |
|
| Number of DNA_PORTs |
0 |
1 |
0% |
|
| Number of DSP48E1s |
0 |
740 |
0% |
|
| Number of EFUSE_USRs |
0 |
1 |
0% |
|
| Number of FRAME_ECCs |
0 |
1 |
0% |
|
| Number of GTPE2_CHANNELs |
0 |
4 |
0% |
|
| Number of IBUFDS_GTE2s |
0 |
8 |
0% |
|
| Number of ICAPs |
0 |
2 |
0% |
|
| Number of IDELAYCTRLs |
0 |
10 |
0% |
|
| Number of IN_FIFOs |
0 |
40 |
0% |
|
| Number of MMCME2_ADVs |
0 |
10 |
0% |
|
| Number of OUT_FIFOs |
0 |
40 |
0% |
|
| Number of PCIE_2_1s |
0 |
1 |
0% |
|
| Number of PHASER_REFs |
0 |
10 |
0% |
|
| Number of PHY_CONTROLs |
0 |
10 |
0% |
|
| Number of PLLE2_ADVs |
0 |
10 |
0% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of XADCs |
0 |
1 |
0% |
|
| Average Fanout of Non-Clock Nets |
1.00 |
|
|
|