Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version3064766
date_generatedWed Mar 24 16:34:51 2021 os_platformLIN64
product_versionVivado v2020.2 (64-bit) project_id62f425ec49554f72885b14ef9271c459
project_iteration1 random_idbcfae8310c755bf7ad97b7045d4a4511
registration_id211070429_0_0_814 route_designTRUE
target_devicexc7a200t target_familyartix7
target_packagefbg484 target_speed-1
tool_flowVivado

user_environment
cpu_nameAMD Ryzen 7 4700U with Radeon Graphics cpu_speed1386.342 MHz
os_nameUbuntu os_releaseUbuntu 20.04.1 LTS
system_ram16.000 GB total_processors1

vivado_usage
gui_handlers
addsrcwizard_specify_hdl_netlist_block_design=1 addsrcwizard_specify_or_create_constraint_files=2 basedialog_ok=14 constraintschooserpanel_create_file=1
createconstraintsfilepanel_file_name=1 createsrcfiledialog_file_name=1 definemodulesdialog_define_modules_and_specify_io_ports=21 filesetpanel_file_set_panel_tree=18
flownavigatortreepanel_flow_navigator_tree=7 fpgachooser_family=1 fpgachooser_fpga_table=1 gettingstartedview_create_new_project=1
hfolderchooserhelpers_up_one_level=1 pacommandnames_auto_update_hier=3 projectnamechooser_choose_project_location=1 projectnamechooser_project_name=1
rdicommands_save_file=3 srcchooserpanel_create_file=1 srcmenu_ip_hierarchy=2
java_command_handlers
addsources=2 newproject=1 runbitgen=2 runimplementation=2
runsynthesis=4 showview=1 viewtaskimplementation=2
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=VHDL srcsetcount=1 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
ibuf=4 lut4=1 obuf=1
pre_unisim_transformation
ibuf=4 lut4=1 obuf=1

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=0 bufgctrl_util_percentage=0.00
bufhce_available=120 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=40 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=20 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=40 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=10 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=10 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=740 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=1 lvcmos15=0
lvcmos18=0 lvcmos25=1 lvcmos33=0 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=365 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=730 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=365 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
ibuf_functional_category=IO ibuf_used=4 lut4_functional_category=LUT lut4_used=1
obuf_functional_category=IO obuf_used=1
slice_logic
f7_muxes_available=66900 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=33450 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=133800 lut_as_logic_fixed=0 lut_as_logic_used=1 lut_as_logic_util_percentage=<0.01
lut_as_memory_available=46200 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=267600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=0 register_as_flip_flop_util_percentage=0.00
register_as_latch_available=267600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=133800 slice_luts_fixed=0 slice_luts_used=1 slice_luts_util_percentage=<0.01
slice_registers_available=267600 slice_registers_fixed=0 slice_registers_used=0 slice_registers_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=133800 lut_as_logic_fixed=0
lut_as_logic_used=1 lut_as_logic_util_percentage=<0.01 lut_as_memory_available=46200 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_driven_from_outside_the_slice_fixed=0 register_driven_from_outside_the_slice_used=0 register_driven_from_within_the_slice_fixed=0 register_driven_from_within_the_slice_used=0
slice_available=33450 slice_fixed=0 slice_registers_available=267600 slice_registers_fixed=0
slice_registers_used=0 slice_registers_util_percentage=0.00 slice_used=1 slice_util_percentage=<0.01
slicel_fixed=0 slicel_used=1 slicem_fixed=0 slicem_used=0
unique_control_sets_available=33450 unique_control_sets_fixed=33450 unique_control_sets_used=0 unique_control_sets_util_percentage=0.00
using_o5_and_o6_fixed=0.00 using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=1
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -lint=default::[not_specified] -max_bram=default::-1
-max_bram_cascade_height=default::-1 -max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1
-mode=default::default -name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified]
-no_timing_driven=default::[not_specified] -os=default::[not_specified] -part=xc7a200tfbg484-1 -resource_sharing=default::auto
-retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified]
-seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3 -top=mustervergleich
-verilog_define=default::[not_specified]
usage
elapsed=00:00:20s hls_ip=0 memory_gain=97.000MB memory_peak=2398.316MB