blinkled Project Status (03/31/2022 - 14:56:33)
Project File: steuerled.xise Parser Errors: No Errors
Module Name: blinkled Implementation State: Synthesized
Target Device: xc3s250e-4tq144
  • Errors:
 No Errors
Product Version:ISE 14.7
  • Warnings:
 No Warnings
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 23 2448 0%
Number of Slice Flip Flops 23 4896 0%
Number of 4 input LUTs 45 4896 0%
Number of bonded IOBs 4 108 3%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentDo. Mrz 31 14:56:33 2022000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 03/31/2022 - 14:56:33