sinus Project Status
Project File: sinus.xise Parser Errors: No Errors
Module Name: sinus Implementation State: Programming File Generated
Target Device: xc3s250e-4tq144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 17 4,896 1%  
Number of 4 input LUTs 79 4,896 1%  
Number of occupied Slices 46 2,448 1%  
    Number of Slices containing only related logic 46 46 100%  
    Number of Slices containing unrelated logic 0 46 0%  
Total Number of 4 input LUTs 87 4,896 1%  
    Number used as logic 79      
    Number used as a route-thru 8      
Number of bonded IOBs 9 108 8%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 4.45      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSo. Mai 28 17:54:25 2023000
Translation ReportCurrentSo. Mai 28 17:54:30 2023000
Map ReportCurrentSo. Mai 28 17:54:32 2023002 Infos (0 new)
Place and Route ReportCurrentSo. Mai 28 17:54:38 2023002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentSo. Mai 28 17:54:39 2023006 Infos (0 new)
Bitgen ReportCurrentSo. Mai 28 17:54:43 2023000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentSo. Mai 28 17:54:44 2023
WebTalk Log FileCurrentSo. Mai 28 17:54:44 2023

Date Generated: 05/29/2023 - 10:39:35