| Project Statistics |
| PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
| PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
| PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store non-default values only |
| PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
| PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
| PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2025-05-05T15:21:13 |
| PROP_intWbtProjectID=6B430BEBE6794A767B204F3E7771628D |
PROP_intWbtProjectIteration=5 |
| PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
| PROP_lockPinsUcfFile=changed |
PROP_AutoTop=true |
| PROP_DevFamily=Spartan3E |
PROP_DevDevice=xc3s250e |
| PROP_DevFamilyPMName=spartan3e |
PROP_DevPackage=tq144 |
| PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
| PROP_PreferredLanguage=Verilog |
FILE_UCF=1 |
| FILE_VHDL=1 |