Transfert Project Status (05/12/2025 - 15:36:45)
Project File: Transfert.xise Parser Errors: No Errors
Module Name: seriellemu_lettres Implementation State: Programming File Generated
Target Device: xc3s250e-4tq144
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 19 4,896 1%  
Number of 4 input LUTs 19 4,896 1%  
Number of occupied Slices 17 2,448 1%  
    Number of Slices containing only related logic 17 17 100%  
    Number of Slices containing unrelated logic 0 17 0%  
Total Number of 4 input LUTs 28 4,896 1%  
    Number used as logic 19      
    Number used as a route-thru 9      
Number of bonded IOBs 2 108 1%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.30      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMo. Mai 12 15:14:17 2025   
Translation ReportCurrentMo. Mai 12 15:14:20 2025   
Map ReportCurrentMo. Mai 12 15:14:23 2025   
Place and Route ReportCurrentMo. Mai 12 15:14:29 2025   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentMo. Mai 12 15:14:30 2025   
Bitgen ReportCurrentMo. Mai 12 15:16:09 2025   
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMo. Mai 12 15:36:45 2025
WebTalk Log FileCurrentMo. Mai 12 15:36:45 2025

Date Generated: 05/12/2025 - 15:36:45