Transfert Project Status (05/12/2025 - 15:36:45)
Project File:	Transfert.xise	Parser Errors:	No Errors
Module Name:	Transfert	Implementation State:	Programming File Generated
Target Device:	xc3s250e-4tq144	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	19	4,896	1%
Number of 4 input LUTs	19	4,896	1%
Number of occupied Slices	17	2,448	1%
Number of Slices containing only related logic	17	17	100%
Number of Slices containing unrelated logic	0	17	0%
Total Number of 4 input LUTs	28	4,896	1%
Number used as logic	19
Number used as a route-thru	9
Number of bonded IOBs	2	108	1%
Number of BUFGMUXs	1	24	4%
Average Fanout of Non-Clock Nets	3.30

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Mo. Mai 12 15:35:18 2025	0	0	0
Translation Report	Current	Mo. Mai 12 15:35:30 2025	0	0	0
Map Report	Current	Mo. Mai 12 15:35:33 2025	0	0	2 Infos (0 new)
Place and Route Report	Current	Mo. Mai 12 15:35:39 2025	0	0	2 Infos (0 new)
Power Report
Post-PAR Static Timing Report	Current	Mo. Mai 12 15:35:40 2025	0	0	6 Infos (0 new)
Bitgen Report	Current	Mo. Mai 12 15:36:44 2025	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Mo. Mai 12 15:36:45 2025
WebTalk Log File	Current	Mo. Mai 12 15:36:45 2025

Date Generated: 05/12/2025 - 15:36:45