NeuroNetzNXOR Project Status (04/16/2025 - 12:59:09)
Project File: NeuroNetzNXOR.xise Parser Errors: No Errors
Module Name: NeuroNetzNXOR Implementation State: Programming File Generated
Target Device: xc3s250e-4tq144
  • Errors:
 No Errors
Product Version:ISE 14.7
  • Warnings:
 No Warnings
Design Goal: Balanced
  • Routing Results:
 All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
 0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 103 4,896 2%  
Number of occupied Slices 56 2,448 2%  
    Number of Slices containing only related logic 56 56 100%  
    Number of Slices containing unrelated logic 0 56 0%  
Total Number of 4 input LUTs 106 4,896 2%  
    Number used as logic 103      
    Number used as a route-thru 3      
Number of bonded IOBs 3 108 2%  
Average Fanout of Non-Clock Nets 2.63      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMi. Apr 16 12:58:53 2025000
Translation ReportCurrentMi. Apr 16 12:58:57 2025000
Map ReportCurrentMi. Apr 16 12:59:00 2025002 Infos (0 new)
Place and Route ReportCurrentMi. Apr 16 12:59:04 2025001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMi. Apr 16 12:59:05 2025006 Infos (0 new)
Bitgen ReportCurrentMi. Apr 16 12:59:09 2025000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMi. Apr 16 12:59:09 2025
WebTalk Log FileCurrentMi. Apr 16 12:59:09 2025

Date Generated: 04/16/2025 - 12:59:09