blinkend Project Status (06/23/2025 - 13:54:52)
Project File: Laufendeslicht.xise Parser Errors: No Errors
Module Name: blinkend Implementation State: Programming File Generated
Target Device: xc3s250e-4tq144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 23 4,896 1%  
Number of 4 input LUTs 14 4,896 1%  
Number of occupied Slices 19 2,448 1%  
    Number of Slices containing only related logic 19 19 100%  
    Number of Slices containing unrelated logic 0 19 0%  
Total Number of 4 input LUTs 37 4,896 1%  
    Number used as logic 14      
    Number used as a route-thru 23      
Number of bonded IOBs 5 108 4%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.30      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMo. Jun 23 13:54:25 2025000
Translation ReportCurrentMo. Jun 23 13:54:29 2025000
Map ReportCurrentMo. Jun 23 13:54:33 2025002 Infos (2 new)
Place and Route ReportCurrentMo. Jun 23 13:54:38 2025002 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportCurrentMo. Jun 23 13:54:40 2025006 Infos (6 new)
Bitgen ReportCurrentMo. Jun 23 13:54:51 2025000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMo. Jun 23 13:54:52 2025
WebTalk Log FileCurrentMo. Jun 23 13:54:52 2025

Date Generated: 06/23/2025 - 13:54:52